`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: CBICR, Tsinghua Univ.
// Engineer: Hongyi Li
// 
// Create Date: 2024/12/23 11:58:54
// Design Name: 
// Module Name: Nearby Virtual Channel Allocation
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module VcAllocNby
#(
    parameter VCNumber  = 'd4
)(
    input                          clk, rst_n,
    input  [5*VCNumber -1:0]       i_credit,
    output [5*VCNumber -1:0]       o_next_vc
);

reg    [5*VCNumber -1:0]   reg_next_vc;
wire   [5*VCNumber -1:0]   wire_next_vc;

assign o_next_vc = reg_next_vc;

genvar i;
generate 
    for (i = 0; i < 5; i = i + 1) begin
        // Arbitor: k [5] -> j [VCNumber]
        RoundRobinArbitor #(
            .N(VCNumber)
        ) VCs_Arb_U (
            .clk(clk), .rst_n(rst_n),
            .i_req(i_credit[VCNumber*(i+1)-1 : VCNumber*i]), 
            .o_grant(wire_next_vc[VCNumber*(i+1)-1 : VCNumber*i])
        );
    end
    always @(posedge clk) begin
        if (~rst_n) 
            reg_next_vc <= 0;
        else
            reg_next_vc <= wire_next_vc;
    end
endgenerate

endmodule